The present invention relates to semiconductor device fabrication, and more particularly, to a variable length, multi-channel semiconductor including self-aligned metal gate stacks.
Recent trends have turned to low-resistive metals as a desired material to form semiconductor device gate stacks. The electrical resistivity of tungsten (W) gate stacks, for example, has shown to be as much as one-hundred times lower than comparably sized doped polysilicon gate stacks. In addition, the larger work function of tungsten and other low-resistive metals produces low and nearly symmetrical threshold voltages for both PMOS and NMOS devices on moderately doped substrates. Accordingly, tungsten and other low-resistive metals are attractive as a gate stack material in CMOS circuit design. Tungsten, for example, has also exhibited the potential to reduce sub-threshold leakage currents and decrease sensitivity to body bias as compared to conventional doped polysilicon gate stacks.
Various semiconductor structures include gate channel regions having varying lengths. For example, CMOS semiconductor devices may include both a narrow gate channel region and a long gate channel region. The long gate channel region, however, may be susceptible to etch loading effects when simultaneously etching the narrow gate channel region. This may cause the long gate channel region to be etched more quickly when simultaneously etching the narrow gate channel region, thereby forming non-uniform gate stacks. Therefore, an additional masking layer is typically required during the fabrication process to protect the long gate channel region from etch loading effects.